FPGA状态机实现序列检测
module reg1
(
input rst,
input clk,
input in,
output reg out0
);
parameter S0=5'b00000;
parameter S1=5'b00001;
parameter S2=5'b00010;
parameter S3=5'b00100;
parameter S4=5'b01000;
parameter S5=5'b10000;
reg [5:0]current_state;
reg [5:0]next_state;
always@(posedge clk or negedge rst)
begin
if(~rst)
current_state<=S0;
else
current_state<=next_state;
end
always@(*)
begin
next_state=S0;
case(current_state)
S0:if(in==1)
next_state=S1;
else
next_state=S0;
S1:if(in==0)
next_state=S2;
else
next_state=S1;
S2:if(in==0)
next_state=S3;
else
next_state=S1;
S3:if(in==1)
next_state=S4;
else
next_state=S0;
S4:if(in==0)
next_state=S5;
else
next_state=S1;
S5:if(in==0)
next_state=S3;
else
next_state=S1;
default:next_state=S0;
endcase
end
always@(posedge clk or negedge rst)
begin
if(~rst)
out0<=1'b0;
else
case(next_state)
S0:
out0<=1'b0;
S1:
out0<=1'b0;
S2:
out0<=1'b0;
S3:
out0<=1'b0;
S4:
out0<=1'b0;
S5:
out0<=1'b1;
default:;
endcase
end
endmodule
//测试
`timescale 1ns/1ns
module reg1text();
reg clk;
reg rst;
reg in;
initial
begin
rst=0;
#100 rst=1;
#10000 $stop;
end
initial
begin
clk=0;
end
always #5 clk<=~clk;
always@(posedge clk or negedge rst)
begin
if(~rst)
in<=0;
else
in<={$random}%2;
end
reg1
reg1_inst
(
.clk(clk),
.rst(rst),
.in(in),
.out0()
);
【FPGA状态机实现序列检测】endmodule
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