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//==================================================================================================
//Filename: system_delay.v
//Created On: 2018-06-05 10:13:37
//Last Modified : 2018-06-05 17:47:41
//Revision:
//
//Description:
//
//
//==================================================================================================`timescale 1ns/1ns
//Delay 30ms for system stable
module system_init_delay(input clk,
input rst_n,
output delay_done,
output pll_rst
//output delay_cnt
);
parameter SYS_DELAY_TOP=24'd256;
//delay_cnt=24'd0;
reg [24:0]delay_cnt=24'd0;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
delay_cnt<=0;
else if(delay_cnt
//==================================================================================================
//Filename: system_ctrl.v
//Created On: 2018-06-05 10:00:38
//Last Modified : 2018-06-05 17:49:27
//Revision:
//
//Description:
//
//
//==================================================================================================
//rst_n sync`timescale 1ns/1ns
module system_ctrl (
input clkin,// Clock
//input clk_en, // Clock Enable
input rst_n,// Asynchronous reset active low
output sys_rst_n,
output clk_ref,
output delay_done
//output [24:0]delay_cnt
);
//pll
wire locked;
sys_pll u_sys_pll (
areset(pll_rst),
inclk0(clkin),
c0(clk),
locked(locked)
);
//wire delay_done;
reg rst_nr1,rst_nr2;
always @(posedge clk)
begin
if(!rst_n)
begin
rst_nr1<=1'b0;
rst_nr2<=1'b0;
end
else
begin
rst_nr1<=1'b1;
rst_nr2<=rst_nr1;
endend//wire delay_done;
system_init_delay #(//.SYS_DEALY_TOP(24'd2_500_000),
.SYS_DELAY_TOP(24'd100)//for test
)
u_system_init_delay(
.clk(clk),
.rst_n(1'b1),
.delay_done(delay_done)
//.delay_cnt(delay_cnt));
assign clk_ref=clk;
assign sys_rst_n=rst_nr2&pll_rst;
//active highendmodule
//==================================================================================================
//Filename: system_ctrl_TB.v
//Created On: 2018-06-05 10:23:49
//Last Modified : 2018-06-05 16:40:18
//Revision:
//
//Description:
//
//
//==================================================================================================`timescale 1ns/1nsmodule system_ctrl_TB();
reg clk;
reg rst_n;
localparam PERIOD=2;
initial
begin
clk=0;
forever #(PERIOD/2)
clk=~clk;
endtask task_reset ();
begin
rst_n=0;
repeat(2)@(negedge clk);
rst_n=1;
end
endtask//system_ctrl_TB
wire clk_ref;
wire sys_rst_n;
wire delay_done;
//wire [24:0]delay_cnt;
system_ctrl u_system_ctrl(
.clk(clk),
.rst_n(rst_n),
//output
.clk_ref(clk_ref),
.sys_rst_n(sys_rst_n),
.delay_done(delay_done)
// .delay_cnt(delay_cnt) );
//system init task
task task_sysinit;
begin end
endtask//test bench
initial
begin
task_sysinit;
task_reset;
rst_n=0;
#89;
rst_n=1;
#191;
rst_n=0;
#83;
rst_n=1;
#319;
rst_n=0;
#13;
rst_n=1;
endendmodule
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